In modern memory system design a controller is typically utilized to control a number of memory banks, each of which may accommodate a multiplicity of memory components. In order to function as an interface between the memory and another system which may seek access to the memory for the storage or retrieval of data, the controller must be configured to control the particular amount and types of memory banks comprising a particular memory system. Memory bank types may differ, for example, by the speed grades of the memory components accommodated thereby or by the architecture of the particular memory bank. A particular memory bank may, for example, utilize eight memory components with four data ports creating a memory bank with thirty two data bits, while another type of memory bank may offer additional data bits for parity error checking by including a ninth memory component in the memory bank architecture. A further type of memory bank may include ten memory components in the memory bank architecture enabling the system to utilize the additional data bits for encoding error correcting check bits.
When designing such memory systems it is desirable to utilize a single common memory controller that is capable of functioning in a memory system in which the number of memory banks may be altered. Additionally, it is further desirable to utilize a single common memory controller that will function with a number of different types of memory banks. A memory system design capable of detecting and accommodating these variations in memory quantity and type would enable the design and manufacture of memory systems with different quantities and types of memory banks, each designed to meet the requirements of a particular memory system application, without the need to match a specific memory controller with each of these memory systems. Moreover, a further advantage which may be derived from such a memory system is the ability for such a system to manage the real-time alteration of the quantity and/or types of memory within a particular memory system without necessitating the replacement of the controller.
Current memory systems accomplish memory presence and type detection via the addition of dedicated presence detection lines for presence detection operations and separate dedicated type detection lines for type detection operations. For example, U.S. Pat. No. 5,164,916 issued to Wu, et al. teaches a memory module sensing method wherein a dedicated presence detection line couples the sense resistors on inserted memory banks, thereby creating a total resistance equivalent to the parallel combination of the sense resistors on the inserted memory modules. An analog sensing scheme is used to convert the parallel resistance to a logic signal which is coupled via the presence detection line to a comparator for sensing the number of memory modules present. As a further example, U.S. Pat. No. 4,787,060 issued to Boudreau, et al. teaches a method for presence and type detection of a memory module, wherein a first signal on a dedicated presence detection line indicates module presence in a first state, and no module presence in a second state. A second signal on a dedicated type detection line indicates the detection of a first type of memory in a first state or a second type of memory in a second state.
These prior art teachings require that as many as two extra dedicated detection lines per memory module (one for presence and one for type detection) be added to the memory system. In a complex memory system including thirty two memory banks, these systems would require the addition of up to sixty four wires. In such a high density memory system space is typically at a premium. The addition of these extra wires may necessitate the use of finer wiring technologies than the wiring technologies that are ordinarily used for memory system assembly, thereby augmenting the complexity and cost of the memory system. Furthermore, the patent to Wu, et al. requires that a comparator be added to the memory system. This additional component is not typically needed in memory system design and further adds to the cost and complexity of the memory system.
Another recent memory system design utilizes identification registers which are selected over the system address bus. The memory system described in U.S. Pat. No. 4,485,437 issued to Kinghorn teaches that a data processing unit may sense the presence of random access memory units (hereinafter "RAMs") on a memory bank by accessing multi-bit identification codes stored in memory registers on each memory bank. These identification codes are accessed via the system address bus, and read over the system data bus. The data processing unit interprets these codes to sense the presence of each memory bank. This design requires that registers are included on each memory bank to enable readout for presence detection which adds to the complexity of the memory system and increases the cost of the memory banks.
U.S. Pat. No. 4,926,314 issued to Dhuey, et al. teaches the use of an algorithm implemented by the system CPU to determine the system memory capacity formed via the insertion of a number of memory modules. Under control of the algorithm the CPU writes data to unique memory locations on the inserted memory modules and subsequently reads the data back looking for either incorrect or repeating values. In this manner the CPU determines the memory capacity of the system, however, the algorithm occupies CPU resources, thereby delaying the execution of other system routines. Moreover, this algorithm would require a significant amount of run time to sense memory presence in higher density memory systems.